1. Field of the Invention
The present invention relates to a multiprocessor system having a plurality of processor cores, and more particularly, to a multiprocessor system having, e.g., a shared memory shared by a plurality of processor cores.
2. Description of the Related Art
Recently, a multiprocessor system that connects a plurality of processor cores via a shared bus has been developed in the expectation that it could greatly improve the processing performance of a computer apparatus. The operation frequency of a processor core tends to be higher every year. However, an external memory (shared memory) used as a main memory is not so fast as the processor core. The gap between the processor core and the external memory is generally filled using a cache memory. In the cache mechanism of a processor core, the processor core incorporates a primary cache.
Snoop caching is known as a system for maintaining the cache coherency of a shared memory system having a hierarchical structure of a shared memory and primary caches. The snoop cache system maintains the cache coherency by causing each primary cache to exchange update information and the like with itself or the primary cache of another processor core.
However, to maintain the coherency, various kinds of processes including bus transaction monitoring, access information transmission, and forced write-back of latest data to the shared memory occur. This deteriorates the performance and power consumption of the multiprocessor system.
In a system without a cache coherency maintaining mechanism by hardware, shared memory access rules for maintaining the coherency are defined. The primary caches comply with the rules, thereby maintaining the coherency. A relationship between the plurality of processor cores creates a situation that impedes coherency maintenance. Verifications in an amount executable by simulations often fail to find violation accesses. Additionally, it is difficult to cause a simulator to reproduce a violation access detected in a multiprocessor system implemented on a chip, and a long time is necessary to specify the problem.
A related technique of this type is disclosed, which executes high-speed data transfer between cache memories while maintaining the cache coherency in a multiprocessor system formed by connecting a plurality of processor cores to a shared memory via a shared bus (Jpn. Pat. Appln. KOKAI Publication No. 9-185547).